The present disclosure relates to integrated circuit design and manufacturing, and more particularly, to sizing and spacing of sub-resolution assist features (SRAFs) added to integrated circuit designs in photolithographic processing.
Sub-resolution assist features (SRAFs) are added to integrated circuit designs to allow lithographically formed structures to be smaller and sharper than the minimum resolution of an exposure system would otherwise allow. Images printed on a photoresist for an isolated lithographic pattern are more sensitive to focus variations than images for a dense lithographic pattern, and such SRAFs are commonly added to main shapes in a photolithographic mask to create a denser environment for robust printing of integrated circuit features. The SRAFs are not intended to be reproduced as distinct features in the photoresist (e.g., they should not print in the photoresist) because SRAFs only perform the function of increasing the focus sharpness of the main shapes of the integrated circuit features that are printed in the photoresist. Therefore, SRAFs can increase the depth of focus or process window, but SRAFs should avoid being formed as separate structures because such structures could transfer to subsequent steps of the chip manufacturing process and cause unintended consequences.
Such integrated circuit designs that include SRAF features are modeled (tested using either a computer simulator, or by being subjected to a portion of a full manufacturing process, such as test patterning layers through different test exposure masks) before actually being manufactured, to allow any design defects to be detected and corrected prior to expending resources manufacturing potentially defective integrated circuit designs. Such test masks that include SRAF features are sometimes referred to as SRAF macros, and it is common to test how the different SRAF configuration affect a given integrated circuit design differently, using tens or hundreds of different SRAF configurations (e.g., different SRAF sizes and spacing). Each one of the different SRAF configuration on the macro utilizes SRAFs having a single and uniform shape, size, and spacing, such that each SRAF test case has SRAFs that are shaped, sized, and/or spaced differently from the other SRAF test case that are applied to the given integrated circuit design. The SRAF test case that produces the sharpest focus, without having the SRAFs print in the photoresist, identifies the best SRAF shape, size, and spacing for the given integrated circuit design. However, such processes require designers to make and expose many different SRAF test cases, and to evaluate many different resulting exposed photoresists.
A SRAF model is the numerical model that feeds the result of a previous exercise with different SRAF test cases, based on which the model will predict what SRAF configuration will print and what will not print. When building SRAF models, it is common to use images that show transition from non-SRAF printing to SRAF printing. Therefore, a large amount of time is spent designing the SRAF model calibration macro (e.g., the different SRAF test cases) and successful testing is not always guaranteed, because many parameters need to be accounted for with the different test case (SRAFs by themselves only, SRAFs combined integrated circuit features, SRAFs affecting one another, etc.). These parameters can include items such as SRAF size, SRAF to integrated circuit main feature size, SRAF to SRAF size. An exemplary factor that prevents such proper “transition printing” when performing SRAF model building, is that the lithographic development process may not be complete, which can prevent design structure information that accurately captures the transition zone from being known at the time of test mask including the different test case is built. Additional failures in transition printing can occur when engineers attempt to capture too many structures at transition printing zone.